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产品展示 您现在的位置:君硅科技 > >>产品展示>>DLP 产品 & MEMS>>
TMS320VC549图片
 产品型号:TMS320VC549
 库存:2000
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 详细介绍

TMS320VC549_德州仪器推出数字信号处理器

TMS320VC549

The TMS320VC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the '549) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The '549 also utilizes a highly specialized instruction set, which is the basis of its operational flexibility and speed.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the '549 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the TMS320VC549 DSP. For additional inion, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional overview and should be used in conjunction with this data sheet.

For the 144-pin TQFP, the letter B in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin names denotes buffered serial port (BSP), where n = 0 or 1 port. The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes time-division multiplexed (TDM) serial port.

The pin assignments table to follow lists each signal quadrant and BGA ball pin number for the 144-pin BGA package.

The '549 signal descriptions table lists each terminal name, function, and operating mode(s).

产品特性
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17-× 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus Holder Feature
  • Address Bus With a Bus Holder Feature
  • Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
  • 192K× 16-Bit Maximum Addressable Memory Space (64K Words Program,
    64K Words Data, and 64K Words I/O)
  • On-Chip ROM with Some Configurable to Program/Data Memory
  • Dual-Access On-Chip RAM
  • Single-Access On-Chip RAM
  • Single-Instruction Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Better Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank Switching
    • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
    • Time-Division Multiplexed (TDM) Serial Port
    • Buffered Serial Port (BSP)
    • 8-Bit Parallel Host Port Interface (HPI)
    • One 16-Bit Timer
    • External-Input/Output (XIO) Off Control to Disable the External Data Bus, Address Bus and Control Signals
  • Software-Programmable Wait-State Generator and Programmable Bank Switching
  • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
  • Time-Division Multiplexed (TDM) Serial Port
  • Buffered Serial Port (BSP)
  • 8-Bit Parallel Host Port Interface (HPI)
  • One 16-Bit Timer
  • External-Input/Output (XIO) Off Control to Disable the External Data Bus, Address Bus and Control Signals
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) for 3.3-V Power Supply)
  • 10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (2.5-V Core)
  • 8.3-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS) for 3.3-V Power Supply (2.5-V Core) (Product Preview Data)
  • Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)
参数parametrics
参数 TMS320VC549
Applications Communications and Telecom Industrial
Operating Systems DSP/BIOS
DSP 1 C54x
DSP Instruction Type Fixed Point
DSP MHz (Max.) 100 120
DSP Peak MMACS 100 120
General Purpose Memory Async SRAM
HPI 1 8-bit HPI
IO Supply (V) 3.3
Operating Temperature Range (C) -40 to 100
Pin/Package 144BGA MICROSTAR 144LQFP
数据表?(1)
标题 类型 大小 (KB) 日期
TMS320VC549 Fixed-Point DSP PDF 863 2004年 10月 19日
应用手册?(2)
标题 类型 大小 (KB) 日期
Migrating from TMS320VC549 to TMS320VC5409 PDF 77 2002年 2月 12日
TPS6010x/TPS6011x Charge Pump PDF 391 1999年 12月 16日
用户指南?(5)
标题 类型 大小 (KB) 日期
TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 PDF 2156 2001年 3月 31日
TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 PDF 1115 2001年 1月 31日
TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 PDF 1096 2001年 1月 31日
TMS320C548/549 Bootloader & ROM Code Examples Techn. Reference PDF 305 2000年 5月 3日
TMS320C54x DSP Applications Guide Reference Set Volume 4 PDF 1293 1996年 10月 1日
白皮书?(1)
标题 类型 大小 (KB) 日期
“Get smart” with TI’s embedded analytics technology PDF 2059 2012年 5月 30日
设计套件与评估板?(1)
培训内容 型号 类型
TMS320C5416 DSP 入门套件 (DSK) TMDSDSK5416 评估模块和开发板
软件?(2)
培训内容 型号 类型
TMS320C54x DSP 库 SPRC099 软件库
TMS320C54x 芯片支持库 SPRC132 软件库
开发工具?(3)
培训内容 型号 类型
XDS560 高性能调试探针 XDS560 JTAG 仿真器/分析器
C54x UNIX 仿真器 TMDS324L551-09 电路设计和仿真
Code Composer Studio (CCS) 集成开发环境 (IDE) CCSTUDIO 软件开发工具、IDE、编译器
模型?(2)
标题 种类 类型 大小 (KB) 日期
VC549 GGU BSDL Model BSDL Model ZIP 4?KB 2002年 5月 9日
VC549 PGE BSDL Model BSDL Model ZIP 4?KB 2002年 5月 9日
订购型号Ordering
型号 状态 温度 (oC) 价格(美元) | Quantity 封装 | 引脚 器件标记 封装数量 | 载体
TMS320VC549GGU-100 ACTIVE -40 to 100 32.65 | 1ku BGA MICROSTAR?(GGU) | 144 -100 DVC549GGU 160
TMS320VC549GGU-120 OBSOLETE -40 to 100 联系客服 BGA MICROSTAR?(GGU) | 144    
TMS320VC549GGU-80 ACTIVE -40 to 100 29.68 | 1ku BGA MICROSTAR?(GGU) | 144 -80 DVC549GGU 160 | EIAJ TRAY (5+1)
TMS320VC549GGUR-80 ACTIVE -40 to 100 30.57 | 1ku BGA MICROSTAR?(GGU) | 144 -80 DVC549GGU 1000 | LARGE T&R
TMS320VC549GGUR100 OBSOLETE -40 to 100 联系客服 BGA MICROSTAR?(GGU) | 144 -100 DVC549GGU  
TMS320VC549PGE-100 ACTIVE -40 to 100 32.65 | 1ku LQFP?(PGE) | 144 -100 TMS320VC549PGE 60
TMS320VC549PGE-120 ACTIVE -40 to 100 39.18 | 1ku LQFP?(PGE) | 144 -120 TMS320VC549PGE 60
TMS320VC549PGE-80 ACTIVE -40 to 100 29.68 | 1ku LQFP?(PGE) | 144 -80 TMS320VC549PGE 60
TMS320VC549PGE100W OBSOLETE -40 to 100 联系客服 LQFP?(PGE) | 144 -100 TMS320VC549PGE  
TMS320VC549PGER-80 OBSOLETE -40 to 100 联系客服 LQFP?(PGE) | 144 -80 TMS320VC549PGE  
TMS320VC549ZGU-100 OBSOLETE -40 to 100 联系客服 BGA MICROSTAR?(ZGU) | 144 -100 DVC549ZGU  
TMS32VC549PGE100G4 ACTIVE -40 to 100 32.65 | 1ku LQFP?(PGE) | 144 -100 TMS320VC549PGE 60

这里所列出的美国报价单仅供预算参考,指美元报价(规定订量的每片美元,美国离岸价),如有修改不再另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。对于特殊批量报价,请与君硅科技 联络。对于评估板和套件的报价是指一个单位价格。

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