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TMS320VC5501图片
 产品型号:TMS320VC5501
 库存:20000
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 详细介绍

TMS320VC5501_德州仪器推出定点数字信号处

The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x? DSP generation CPU processor core. The C55x? DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x? CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 5501 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Two full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is an 8-bit parallel interface used to provide host processor access to 16K words of internal memory on the 5501. The HPI operates in multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included.

The 5501 is supported by the industry's award-winning eXpressDSP?, Code Composer Studio? Integrated Development Environment (IDE), DSP/BIOS?, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio× IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX?, XDS510? emulation device drivers, and evaluation modules. The 5501 is also supported by the C55x? DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

产品特性
  • High-Performance, Low-Power, Fixed-Point TMS320C55x? Digital Signal Processor (DSP)
    • 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
    • 16K-Byte Instruction Cache (I-Cache)
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
  • 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
  • 16K-Byte Instruction Cache (I-Cache)
  • One/Two Instructions Executed per Cycle
  • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
  • Two Arithmetic/Logic Units (ALUs)
  • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
  • Instruction Cache (16K Bytes)
  • 16K × 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes)
  • 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst RAM (SBRAM)
  • Asynchronous Static RAM (SRAM)
  • Asynchronous EPROM
  • Synchronous DRAM (SDRAM)
  • Synchronous Burst RAM (SBRAM)
  • Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Six-Channel Direct Memory Access (DMA) Controller
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Analog Phase-Locked Loop (APLL) Clock Generator
    • General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
    • 8-Bit Parallel Host-Port Interface (HPI)
    • Four Timers
      • Two 64-Bit General-Purpose Timers
      • 64-Bit Programmable Watchdog Timer
      • 64-Bit DSP/BIOS? Counter
    • Inter-Integrated Circuit (I2C) Interface
    • Universal Asynchronous Receiver/ Transmitter (UART)
  • Six-Channel Direct Memory Access (DMA) Controller
  • Two Multichannel Buffered Serial Ports (McBSPs)
  • Programmable Analog Phase-Locked Loop (APLL) Clock Generator
  • General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
  • 8-Bit Parallel Host-Port Interface (HPI)
  • Four Timers
    • Two 64-Bit General-Purpose Timers
    • 64-Bit Programmable Watchdog Timer
    • 64-Bit DSP/BIOS? Counter
  • Two 64-Bit General-Purpose Timers
  • 64-Bit Programmable Watchdog Timer
  • 64-Bit DSP/BIOS? Counter
  • Inter-Integrated Circuit (I2C) Interface
  • Universal Asynchronous Receiver/ Transmitter (UART)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
    • 201-Terminal MicroStar BGA? (Ball Grid Array) (GZZ and ZZZ Suffixes)
  • 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
  • 201-Terminal MicroStar BGA? (Ball Grid Array) (GZZ and ZZZ Suffixes)
  • 3.3-V I/O Supply Voltage
  • 1.26-V Core Supply Voltage
参数parametrics
参数 TMS320VC5501
Applications Audio Automotive Communications and Telecom Consumer Electronics Industrial
Operating Systems DSP/BIOS VLX
DSP 1 C55x
DSP Instruction Type Fixed Point
DSP MHz (Max.) 300
DSP Peak MMACS 600
On-Chip L1 Cache 16 KB (DSP)
General Purpose Memory 1 32-bit(Async SRAM,SBSRAM)
DRAM SDRAM
UART (SCI) 1
I2C 1
HPI 1 8-bit HPI
McBSP 2
DMA (Ch) 6-Ch
IO Supply (V) 3.3
Operating Temperature Range (C) -40 to 85
Pin/Package 176LQFP 201BGA MICROSTAR
数据表?(1)
标题 类型 大小 (KB) 日期
TMS320VC5501 Fixed-Point Digital Signal Processor PDF 2364 2008年 11月 20日
勘误表?(1)
标题 类型 大小 (KB) 日期
TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata PDF 305 2007年 6月 22日
应用手册?(4)
标题 类型 大小 (KB) 日期
Using the TMS320VC5501/5502 Bootloader PDF 439 2004年 10月 19日
TMS320VC5501 Hardware Designer's Resource Guide PDF 176 2004年 7月 22日
Achieving Efficient Memory System Performance w/ I-Cache on the TMS320VC5501/02 PDF 265 2004年 6月 24日
TMS320VC5501/02 Power Consumption Summary 多种文件格式   2004年 1月 15日
用户指南?(12)
标题 类型 大小 (KB) 日期
TMS320C55x DSP Peripherals Overview Reference Guide PDF 174 2011年 12月 15日
TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG PDF 256 2005年 10月 17日
TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide PDF 510 2005年 8月 22日
TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide PDF 1288 2005年 4月 14日
TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide PDF 356 2005年 3月 24日
TMS320C55x DSP CPU Programmer's Reference Supplement PDF 408 2005年 2月 24日
TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide PDF 490 2004年 11月 12日
TMS320VC5501/5502 DSP Instruction Cache Reference Guide PDF 234 2004年 6月 16日
TMS320VC5501/5502 DSP Timers Reference Guide PDF 367 2004年 4月 19日
TMS320C55x DSP CPU Reference Guide PDF 1096 2004年 2月 25日
TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) RG PDF 290 2003年 12月 30日
TMS320C55x DSP Mnemonic Instruction Set Reference Guide PDF 2328 2002年 10月 11日
白皮书?(1)
标题 类型 大小 (KB) 日期
“Get smart” with TI’s embedded analytics technology PDF 2059 2012年 5月 30日
设计套件与评估板?(2)
培训内容 型号 类型
TMS320VC5509A DSP 入门套件 (DSK) TMDSDSK5509 评估模块和开发板
TMS320VC5510 DSP 入门套件 (DSK) TMDSDSK5510 评估模块和开发板
软件?(5)
培训内容 型号 类型
DSP/BIOS II 实时内核 DSPBIOS DSP/BIOS 实时内核
用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER TELECOMLIB 应用软件与框架
TMS320C55x DSP 库 SPRC100 软件库
TMS320C55x 图像库 SPRC101 软件库
编解码器 - 针对 C55x 器件进行了优化 C55XCODECS 软件编解码器
开发工具?(3)
培训内容 型号 类型
XDS100 低成本调试探针 XDS100 JTAG 仿真器/分析器
XDS560 高性能调试探针 XDS560 JTAG 仿真器/分析器
Code Composer Studio (CCS) 集成开发环境 (IDE) CCSTUDIO 软件开发工具、IDE、编译器
模型?(4)
标题 种类 类型 大小 (KB) 日期
C5501 GZZ BSDL Model BSDL Model ZIP 6?KB 2004年 5月 17日
C5501 PGF BSDL Model BSDL Model ZIP 6?KB 2004年 5月 17日
订购型号Ordering
型号 状态 温度 (oC) 价格(美元) | Quantity 封装 | 引脚 器件标记 封装数量 | 载体
TMS320VC5501GZZ300 ACTIVE -40 to 85 4.92 | 1ku BGA MICROSTAR?(GZZ) | 201 320VC5501GZZ TMS 300 126
TMS320VC5501PGF300 ACTIVE -40 to 85 4.92 | 1ku LQFP?(PGF) | 176 320VC5501PGF TMS 300 40
TMS320VC5501ZZZ300 ACTIVE -40 to 85 4.92 | 1ku BGA MICROSTAR?(ZZZ) | 201 320VC5501ZZZ TMS 300 126
TMX320VC5501GZZ300 OBSOLETE -40 to 85 联系客服 BGA MICROSTAR?(GZZ) | 201    
TMX320VC5501PGF300 OBSOLETE -40 to 85 联系客服 LQFP?(PGF) | 176    

这里所列出的美国报价单仅供预算参考,指美元报价(规定订量的每片美元,美国离岸价),如有修改不再另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。对于特殊批量报价,请与君硅科技 联络。对于评估板和套件的报价是指一个单位价格。

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