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产品展示 您现在的位置:君硅科技 > >>产品展示>>DLP 产品 & MEMS>>
TMS320VC5509A图片
 产品型号:TMS320VC5509A
 库存:2000
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 详细介绍

TMS320VC5509A_德州仪器推出定点数字信号处

TMS320VC5509A

The TMS320VC5509A fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x? DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel interface using the asynchronous EMIF. Serial is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals and three McBSPs.

The 5509A peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5509A. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5509A is supported by the industry‘s award-winning eXpressDSP?, Code Composer Studio? Integrated Development Environment (IDE), DSP/BIOS?, Texas Instruments’ algorithm standard, and the industry‘s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX?, XDS510? emulation device drivers, and evaluation modules. The 5509A is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

The TMS320C55x DSP core was created with an open architecture that allows the addition of application-specific hardware to boost performance on specific algorithms. The hardware extensions on the 5509A strike the perfect balance of fixed function performance with programmable flexibility, while achieving low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The extensions allow the 5509A to deliver exceptional video codec performance with more than half its bandwidth available for performing additional functions such as color space conversion, user-interface operations, security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5509A DSP can power most portable digital video applications with processing headroom to spare. For more inion, see the TMS320C55x Hardware Extensions for Image/Video Applications Programmer‘s Reference (literature number SPRU098). For more inion on using the the DSP Image Processing Library, see the TMS320C55x Image/Video Processing Library Programmer‘s Reference (literature number SPRU037).

产品特性
  • High-Performance, Low-Power, Fixed-Point TMS320C55? Digital Signal Processor
    • 9.26-, 6.95-, 5-ns Instruction Cycle Time
    • 108-, 144-, 200-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 9.26-, 6.95-, 5-ns Instruction Cycle Time
  • 108-, 144-, 200-MHz Clock Rate
  • One/Two Instruction(s) Executed per Cycle
  • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
  • Two Arithmetic/Logic Units (ALUs)
  • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 128K × 16-Bit On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
    • 192K Bytes of Single-Access RAM (SARAM) 24 Blocks of 4K × 16-Bit
  • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
  • 192K Bytes of Single-Access RAM (SARAM) 24 Blocks of 4K × 16-Bit
  • 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
  • 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-Bit External Parallel Bus Memory Supporting Either:
    • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
      • Asynchronous Static RAM (SRAM)
      • Asynchronous EPROM
      • Synchronous DRAM (SDRAM)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
  • Asynchronous Static RAM (SRAM)
  • Asynchronous EPROM
  • Synchronous DRAM (SDRAM)
  • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Scan-Based Emulation Logic
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Watchdog Timer
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Serial Ports Supporting a Combination of:
      • Up to 3 Multichannel Buffered Serial Ports (McBSPs)
      • Up to 2 MultiMedia/Secure Digital CardInterfaces
    • Programmable Phase-Locked Loop Clock Generator
    • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
    • USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers
    • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
    • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
    • 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit Successive Approximation A/D
  • Two 20-Bit Timers
  • Watchdog Timer
  • Six-Channel Direct Memory Access (DMA) Controller
  • Three Serial Ports Supporting a Combination of:
    • Up to 3 Multichannel Buffered Serial Ports (McBSPs)
    • Up to 2 MultiMedia/Secure Digital CardInterfaces
  • Up to 3 Multichannel Buffered Serial Ports (McBSPs)
  • Up to 2 MultiMedia/Secure Digital CardInterfaces
  • Programmable Phase-Locked Loop Clock Generator
  • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
  • USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers
  • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
  • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
  • 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit Successive Approximation A/D
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
    • 179-Terminal MicroStar BGA? (Ball Grid Array) (GHH and ZHH Suffixes)
    • 179-Terminal Lead-Free MicroStar BGA? (Ball Grid Array) (ZHH Suffix)
  • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 179-Terminal MicroStar BGA? (Ball Grid Array) (GHH and ZHH Suffixes)
  • 179-Terminal Lead-Free MicroStar BGA? (Ball Grid Array) (ZHH Suffix)
  • 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os
  • 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
  • 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os
参数parametrics
参数 TMS320VC5509A
DSP MHz (Max.) 200 144 108
USB 1
MMC/SD 2
ADC 1
I2C 1
HPI 1 16-Bit EHPI
McBSP 3
DMA (Ch) 6-Ch
IO Supply (V) 2.7 to 3.6
Operating Temperature Range (C) -40 to 85
Pin/Package 144LQFP 179BGA MICROSTAR
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数据表?(1)
标题 类型 大小 (KB) 日期
TMS320VC5509A Fixed-Point Digital Signal Processor PDF 2007 2008年 1月 22日
勘误表?(1)
标题 类型 大小 (KB) 日期
TMS320VC5509A Digital Signal Processor Silicon Errata (Silicon Revs 1.0 and 1.1) PDF 160 2010年 9月 20日
应用手册?(13)
标题 类型 大小 (KB) 日期
USB 2.0 板载设计及布线指南 (Rev. A) PDF 280 2013年 7月 26日
USB 2.0 Board Design and Layout Guidelines PDF 807 2015年 3月 17日
Board and System Design Considerations for the TMS320VC5503/06/07/09A DSPs PDF 120 2008年 11月 19日
Using the TMS320VC5506/C5507/C5509/C5509A USB Bootloader 多种文件格式   2008年 10月 1日
Programming the TMS320VC5503/C5506/C5507/C5509/C5509A I2C Peripheral 多种文件格式   2008年 9月 26日
Disabling the Internal Oscillator on the TMSVC5503/C5506/C5507/C5509/C5509A DSP PDF 99 2008年 9月 9日
Using the USB APLL on the TMS320VC5506/C5507/C5509A 多种文件格式   2008年 9月 9日
Using the TMS320VC5503/C5506/C5507/C5509/C5509A Bootloader PDF 222 2008年 9月 5日
TMS320VC5503/VC5506/VC5507/C5509A Power Consumption Summary 多种文件格式   2008年 9月 5日
Recommended Power Solutions For TMS320C5509A/07/03 PDF 37 2005年 3月 28日
TMS320VC5509 to TMS320VC5509A Migration PDF 180 2004年 9月 10日
TMS320VC5509A DSP Hardware Designer's Resource Guide PDF 197 2004年 6月 29日
Programming the TMS320VC5509 Multi Media Controller in Native Mode 多种文件格式   2003年 6月 6日
用户指南?(15)
标题 类型 大小 (KB) 日期
TMS320C55x DSP Peripherals Overview Reference Guide PDF 174 2011年 12月 15日
TMS320VC5503/5507/5509 DSP Host Port Interface (HPI) Reference Guide PDF 112 2009年 6月 11日
TMS320VC5509 DSP MultiMediaCard / SD Card Controller Reference Guide PDF 228 2007年 9月 30日
TMS320VC5503/5507/5509/5510 Direct Memory Access(DMA) Controller Reference Guide PDF 342 2007年 1月 9日
TMS320VC5503/5507/5509/5510 DSP Timers Reference Guide PDF 248 2006年 4月 11日
TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG PDF 256 2005年 10月 17日
TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide PDF 1288 2005年 4月 14日
TMS320C55x DSP CPU Programmer's Reference Supplement PDF 408 2005年 2月 24日
TMS320C55x Chip Support Library API Reference Guide PDF 1205 2004年 9月 15日
TMS320VC5507/5509 DSP Universal Serial Bus (USB) Module Reference Guide PDF 761 2004年 6月 25日
TMS320VC5503/5507/5509 DSP Real-Time Clock (RTC) Reference Guide PDF 236 2004年 6月 25日
TMS320VC5507/5509 DSP Analog-to-Digital Converter (ADC) Reference Guide PDF 102 2004年 6月 25日
TMS320VC5503/5507/5509 DSP External Memory Interface (EMIF) Reference Guide PDF 570 2004年 6月 4日
TMS320C55x DSP CPU Reference Guide PDF 1096 2004年 2月 25日
TMS320C55x DSP Mnemonic Instruction Set Reference Guide PDF 2328 2002年 10月 11日
选择与解决方案指南?(1)
标题 类型 大小 (KB) 日期
TI HealthTech Fitness Guide PDF 3594 2013年 4月 10日
白皮书?(1)
标题 类型 大小 (KB) 日期
“Get smart” with TI’s embedded analytics technology PDF 2059 2012年 5月 30日
设计文件?(2)
标题 类型 大小 (KB) 日期
TMS320VC5509A (PGE designator) ORCAD Symbol ZIP 6 2004年 6月 9日
TMS320VC5509A (GHH designator) ORCAD Symbol ZIP 7 2004年 6月 9日
设计套件与评估板?(2)
培训内容 型号 类型
TMS320VC5509A DSP 入门套件 (DSK) TMDSDSK5509 评估模块和开发板
TMS320VC5510 DSP 入门套件 (DSK) TMDSDSK5510 评估模块和开发板
软件?(5)
培训内容 型号 类型
DSP/BIOS II 实时内核 DSPBIOS DSP/BIOS 实时内核
用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER TELECOMLIB 应用软件与框架
TMS320C55x DSP 库 SPRC100 软件库
TMS320C55x 图像库 SPRC101 软件库
编解码器 - 针对 C55x 器件进行了优化 C55XCODECS 软件编解码器
开发工具?(3)
培训内容 型号 类型
XDS100 低成本调试探针 XDS100 JTAG 仿真器/分析器
XDS560 高性能调试探针 XDS560 JTAG 仿真器/分析器
Code Composer Studio (CCS) 集成开发环境 (IDE) CCSTUDIO 软件开发工具、IDE、编译器
模型?(4)
标题 种类 类型 大小 (KB) 日期
VC5509A PGE BSDL Model BSDL Model ZIP 6?KB 2006年 6月 6日
VC5509A GHH BSDL Model BSDL Model ZIP 6?KB 2006年 6月 6日
订购型号Ordering
型号 状态 温度 (oC) 价格(美元) | Quantity 封装 | 引脚 器件标记 封装数量 | 载体
TMS320VC5509AGHH ACTIVE -40 to 85 15.72 | 1ku BGA MICROSTAR?(GHH) | 179 VC5509AGHH TMS320 160
TMS320VC5509AGHHAU OBSOLETE   联系客服 BGA MICROSTAR?(GHH) | 179 VC5509AGHHAU TMS320  
TMS320VC5509AGHHR ACTIVE -40 to 85 15.72 | 1ku BGA MICROSTAR?(GHH) | 179 VC5509AGHH TMS320 1000 | LARGE T&R
TMS320VC5509APGE ACTIVE -40 to 85 15.72 | 1ku LQFP?(PGE) | 144 VC5509APGE TMS320 60
TMS320VC5509APGER OBSOLETE -40 to 85 联系客服 LQFP?(PGE) | 144    
TMS320VC5509AZHH ACTIVE -40 to 85 15.72 | 1ku BGA MICROSTAR?(ZHH) | 179 VC5509AZHH TMS320 160
TMS320VC5509AZHHR ACTIVE -40 to 85 15.72 | 1ku BGA MICROSTAR?(ZHH) | 179 VC5509AZHH TMS320 1000 | LARGE T&R
TMX320VC5509APGE OBSOLETE -40 to 85 联系客服 LQFP?(PGE) | 144    

这里所列出的美国报价单仅供预算参考,指美元报价(规定订量的每片美元,美国离岸价),如有修改不再另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。对于特殊批量报价,请与君硅科技 联络。对于评估板和套件的报价是指一个单位价格。

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